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Open Access Research

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Chengen Yang*, Yunus Emre, Yu Cao and Chaitali Chakrabarti

Author Affiliations

School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287, USA

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EURASIP Journal on Advances in Signal Processing 2012, 2012:211  doi:10.1186/1687-6180-2012-211

Published: 3 October 2012

Abstract

Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10–8. For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10–8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

Keywords:
MLC PRAM; STT-RAM; Circuit level techniques; Error control coding; Block failure rate