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This article is part of the series Coding and Signal Processing for Non-Volatile Memories.

Open Access Research

Verify level control criteria for multi-level cell flash memories and their applications

Yongjune Kim1, Jaehong Kim2, Jun Jin Kong2, B V K Vijaya Kumar1* and Xin Li1

Author Affiliations

1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213, USA

2 Samsung Electronics Co., Ltd., Gyeonggi-do, 445-701, Hwasung, Korea

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EURASIP Journal on Advances in Signal Processing 2012, 2012:196  doi:10.1186/1687-6180-2012-196

The electronic version of this article is the complete one and can be found online at: http://asp.eurasipjournals.com/content/2012/1/196

Received:14 April 2012
Accepted:17 August 2012
Published:5 September 2012

© 2012 Kim et al.; licensee Springer.

This is an Open Access article distributed under the terms of the Creative Commons Attribution License ( http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In 1M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.


Flash memory is now the fastest growing memory segment, driven by the rapid growth of mobile devices and solid state drives (SSD). To satisfy the market demand for lower cost per bit and higher density of nonvolatile memory, there are two approaches: (1) technology scaling, (2) multi-level cell (MLC) [1-4].

As the technology continues to scale down, flash memories suffer from more severe physical degradation mechanisms such as cell-to-cell interference (coupling) and charge leakage [5,6]. In addition, M-bit/cell MLC flash memories have 2M states within the threshold voltage window whereas the single-level cell (SLC) has only two states. Therefore, the reliability of stored data is an important challenge for high density flash memories.

In order to cope with this reliability problem, many approaches have been proposed. The incremental step pulse programming (ISPP), which is the most widely used programming scheme, was proposed to maintain a tight cell threshold voltage distribution for high reliability [7,8]. ISPP is a program and verify strategy with a stair case program voltage Vpp as illustrated in Figure 1, where ΔVpp is the incremental step size. During each program and verify cycle, the floating gate threshold voltage is first boosted by up to ΔVpp and then compared with the corresponding verify level. If the threshold voltage of the memory cell is still lower than the verify level, the program and verify iteration continues. Otherwise, further programming of this cell is disabled [7-10].

thumbnailFigure 1. Program pulses in ISPP. A verify operation is carried out after each pulse. ΔVpp is the incremental step size of the program pulse. Vpp0 is the initial value of the program pulse. Tverify is the verify read time. Tpulse is the program pulse width [10].

Therefore, positions of program states (except the erase state) are determined by verify levels and the tightness of each program state depends on the incremental step size ΔVpp. By reducing ΔVpp, the cell threshold voltage distribution can be made tighter, but the programming time will increase [7,8]. In brief, ISPP can control both the distances between states by verify levels and the tightness of program states by the incremental step size.

For SLC, determining the verify level of the programming state is a simple problem because there is only one program state and the margin between the erase state and the program state is sufficiently large so that small changes in the margin will not change the error rates noticeably. However, the verify level control issue for M-bit/cell flash memories is more important and complex than that for SLC. This is because 2M states have to be crammed within the given constrained threshold voltage window W . More states will significantly reduce the margin between states and bit error rates (BER) will vary in response to small changes in verify levels. Furthermore, the number of verify levels which ISPP has to control increases from 1 (for SLC) to 2M−1 (for M-bit/cell MLC). In addition, as explained in the following, the multipage architecture of MLC flash memories makes verify level control more complex than SLC.

Most MLC flash memories adopt the multipage architecture. The important property of the multipage architecture is that different bits of a single cell are assigned into different pages [10-15]. Therefore, BERs of each page can be different. As a page is the unit of data that is programmed and read at one time, the error control coding (ECC) should be applied within the same page. It means that each page is composed of one or several codewords. Therefore, ECC has to be designed for the worst page BER and this leads to wasted redundancy for the other (i.e., better) pages. This uneven page BER problem is an important and practical issue and there have been several attempts to deal with it [11-15].

To deal with this different page BERs issue, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER. The second criterion is to make all page BERs equal [14]. These two criteria will be formulated as convex optimization problems. After solving these optimization problems, we will compare the numerical results from two criteria. In addition, the advantages and disadvantages of the two criteria will be discussed based on reliability, speed performance, and architecture of MLC flash memories. To the best of authors’ knowledge, the convex optimization approach for verify levels of ISPP has not been addressed in the open literature though experimental approaches could be investigated in industry.

An interesting way to combine the speed advantage of SLC and the cost advantage of MLC is to use a hybrid solid state drive (SSD) that judiciously uses both SLC and MLC flash memories. The basic idea of hybrid SSD is to complement the drawbacks of SLC and MLC with each other’s advantages [16-19]. Based on the architecture of the hybrid SSD and properties of the proposed verify level control criteria, we propose a strategy to apply the proper verify level control criterion for the hybrid SSD. This strategy is aimed at both reliability and speed performance.

The rest of this article is organized as follows: Section “Cell threshold voltage distribution” discusses the cell threshold voltage distribution under the assumption of a Gaussian mixture model (GMM). Based on this statistical model, the overall BER and the page BER are derived. Sections “Criteria for verify level control” and “ECC and flash memories of multipage architecture” address verify level control criteria and discuss their advantages and disadvantages for various MLCs (M = 2 ∼ 4) considering multipage architecture and ECC. Section “Hybrid SSD and strategy for verify level control” proposes a method to choose these criteria for the hybrid SSD based on reliability and speed performance. Finally, Section “Conclusion” concludes this article.

Cell threshold voltage distribution

In M-bit/cell flash memory, the cell threshold voltage distribution is composed of 2M states from S0 (the erase state) to S2M−1 (the highest state). Even though there are tail cells and asymmetry in cell distributions, the cell threshold voltage distribution of flash memories could be approximated as a sum of Gaussian distributions [6,20,21]. Therefore, we will model the cell threshold voltage distribution f(x) by the following GMM.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M1','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M1">View MathML</a>


where x refers to the threshold voltage and fi(x) is a Gaussian pdf with mean μi and standard deviation σi corresponding to the state Si. P(Si) is the probability of the state Si. If data size is sufficiently large and a scrambler is used, then we can assume that <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M2','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M2">View MathML</a> with high probability.

Figure 2 shows the cell distribution of 2-bit/cell flash memories. There are four states from S0 (the erase state) to S3(the highest state) within the constrained voltage window W . The constrained voltage window W is the distance between the mean of the erase state and the mean of the highest state, which is given by

thumbnailFigure 2. Cell threshold voltage distribution for 2-bit/cell flash memories. There are four states from S0 to S3. Each state Si can be modeled by the distribution fi.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M3','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M3">View MathML</a>


The overall BER (i.e., BERoverall) is the total number of erroneous bits divided by the total number of data bits which contains data of all pages. If the Gray mapping is used, there is only one bit difference between Si and Si + 1. For example, in 2-bit/cell MLC, states S0, S1, S2, and S3 denote bit patterns 11, 10, 00, and 01. Probabilities that cells are misread as states which are more than two states away from the original state are much smaller than probabilities of cells being misread as adjacent states and thus are negligible. Therefore, the overall BER can be expressed as

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M4','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M4">View MathML</a>


where Δi,1 is the distance from μi to Di,i + 1 and Δi + 1,0 is the distance from μi + 1 to Di,i + 1. Di,i + 1 is the optimal decision level between Si and Si + 1, which satisfies the condition of fi(Di,i + 1) = fi + 1(Di,i + 1) [22-24]. In addition, σi,0 and σi,1 are used separately for convenience although σi,0 = σi,1 = σi. The tail probability function Q(x) is defined as

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M5','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M5">View MathML</a>


If we change the index of Δi,j into Δk and σi,j into ρk by k =2 i + j, (3) can be rewritten as

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M6','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M6">View MathML</a>


where all Δk s are positive since it is natural that μi + 1 > μi.

Most MLC flash memories adopt multipage architectures [10]. In this multipage architecture, ECC encoding and decoding are performed within each page. This means that pages with higher BERs will suffer from worse decoding failure rate. Therefore, the BER of each page could be more important than the overall BER in terms of ECC [11,13-15].

The page BER (i.e., the BER of each page) depends on the mapping scheme that converts a state level to corresponding bit representation. We will define BERpage m as the BER of page m. For example, if the 2-bit/cell flash memory adopts the Gray mapping of Table 1, the data of page 1 are obtained by one read operation between S1 and S2. Therefore, the BER of page 1 is determined by f1(x) and f2(x). In order to read the data of page 2, two read operations (one between S0 and S1, and another between S2 and S3) are required. Then the BER of page 2 is determined by f0(x) and f1(x), f2(x), and f3(x). Therefore, page BERs for 2-bit/cell are given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M7','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M7">View MathML</a>


Table 1. Gray mapping for 2-bit/cell flash memories

By the same method, page BERs for 3-bit/cell adopting the Gray mapping of Table 2 are given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M8','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M8">View MathML</a>


Table 2. Gray mapping for 3-bit/cell flash memories

Similarly, page BERs for 4-bit/cell or more could be derived from the mapping scheme provided.

The overall BER of (3) can be expressed as the mean of page BERs, which is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M9','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M9">View MathML</a>


The distance between the means of Si and Si + 1 is μi + 1 μi = Δi,1 + Δi + 1,0. We will term μi + 1 μi as the distance from Si to Si + 1, and the distance from Si to Si + 1 will be determined by Δi,1 and Δi + 1,0. For all states, we will define two parameters as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M10','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M10">View MathML</a>


<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M11','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M11">View MathML</a>


where Δk = Δi,j and ρk = σi,j by k = 2i + j. Therefore, <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M12','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M12">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M13','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M13">View MathML</a> will represent the all distances between states and the tightness of program states, respectively, and they will determine the overall BER and the page BERs. In the ISPP scheme, <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M14','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M14">View MathML</a> can be controlled by verify levels and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M15','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M15">View MathML</a> by the incremental step size. In the following section, we will propose criteria for verify level control, which means how to determine <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M16','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M16">View MathML</a> at the given <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M17','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M17">View MathML</a>.

Criteria for verify level control

We investigate two verify level control criteria. The first criterion is to minimize the overall BER, which is aimed at only reliability. The second criterion is to make page BERs equal considering both the reliability and the multipage architecture. These two criteria will be formulated as optimization problems. If the parameters of W(=μ2M−1μ0) and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M18','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M18">View MathML</a> are given, <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M19','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M19">View MathML</a> will be the variables of optimization problems.

We will show that the proposed criteria for verify level control are convex optimization problems. Therefore, the (globally) optimal solution can be efficiently found using numerical optimization techniques and the interior-point method was used to obtain the numerical results [25]. Also, mathematical conditions for the optimal solutions of these criteria are derived.

Criterion 1: minimize overall BER

The first criterion is to minimize the overall BER. This criterion 1 for M-bit/cell flash memories can be formulated as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M20','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M20">View MathML</a>


where <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M21','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M21">View MathML</a> BERoverall by (5).

The cost function g1(·) is a nonnegative weighted sum of Q(·). From (4), the second derivative of Q(·) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M22','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M22">View MathML</a>


Since Δk is the distance and ρk is the standard deviation, all Δks and ρks are always positive. Therefore, (11) is a convex optimization problem and can be solved by several numerical methods [25].

We will define the Lagrangian G1 as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M23','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M23">View MathML</a>


where <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M24','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M24">View MathML</a>. The optimal solution of (11) has to satisfy the following Karush-Kuhn-Tucker (KKT) conditions [25].

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M25','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M25">View MathML</a>


Since all Δks are positive, ηk = 0 for all k by (14), which results from complementary slackness. Therefore, the optimal solution will satisfy the following condition from (13) and (14).

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M26','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M26">View MathML</a>


From (15), the optimal solution has to satisfy the following condition in order to minimize the overall BER.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M27','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M27">View MathML</a>


Figure 3 illustrates the condition of (16) for minimizing the overall BER. In addition, Figure 3 shows that the decision level Di,i + 1 satisfies the condition fi(Di,i + 1) = fi + 1(Di,i + 1) which corresponds to the definition of the optimal decision level [22-24].

thumbnailFigure 3. Example of criterion 1 for 2-bit/cell. This example illustrates the condition which minimizes the overall BER.

If variances for all states are equal (i.e., <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M28','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M28">View MathML</a>), then all Δks become <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M29','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M29">View MathML</a> from (11) and (15). In this case, the BER of page m (1 ≤ m M) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M30','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M30">View MathML</a>


(17) shows that BERpage m+1 will be twice BERpage m if variances for all states are same. When M = 2, BERpage 1<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M31','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M31">View MathML</a> and BERpage 2 = <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M32','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M32">View MathML</a>. From (8), BERoverall = <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M33','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M33">View MathML</a>. Figure 4 shows BERpage 1, BERpage 2, and BERoverall as a function of σ for 2-bit/cell flash memories. From (17), it is seen that the ratio of page BERs for 3-bit/cell is 1:2:4. For 4-bit/cell flash memories, the ratio of page BERs will be 1:2:4:8 [11-15]. Therefore, using criterion 1 makes the difference between page BERs larger as M increases.

thumbnailFigure 4. BER of 2-bit/cell flash memories using Criterion 1. The constrained voltage window W is assumed to be 5.

In addition, the difference between page BERs from criterion 1 could increase if variances for states are not equal. For example, it is possible that the erase state S0 has wider distribution than other program states since the cell threshold voltage distribution of the erase state is not controlled as tightly as other program states by ISPP [8]. In this case, more errors will occur between S0 and S1, which results in the increase of the last page BER (BERpage M) in the Gray mapping schemes of Tables 13. Table 4 shows the increase of the difference between page BERs. In Table 4, we assumed that the standard deviation of the erase state (S0) is σ0 and standard deviations of other program states (S1S3) are same as σ. As the erase state distribution becomes broader, criterion 1 will lead to more difference between page BERs.

Table 3. Gray mapping for 4-bit/cell flash memories

Table 4. BERpage 2/BERpage 1 for 2-bit/cell flash memories (W = 5)

Criterion 2: make page BERs equal

The second criterion is to make the page BERs equal [14]. In addition, the overall BER has to be made as small as possible. Therefore, this criterion 2 for M-bit/cell flash memories can be formulated as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M34','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M34">View MathML</a>


where <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M35','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M35">View MathML</a> BERpage m. Therefore, from the constraints of this optimization problem, ε will represent the maximum value among all page BERs. While trying to minimize ε, we can find the optimal solution which minimizes the overall BER among candidates satisfying the following condition.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M36','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M36">View MathML</a>


In other words, even though the formulation in (18) does not explicitly set the page BERs to be identical, it implicitly minimizes the difference between all page BERs. Intuitively, if BERpage m is higher than other page BERs, the optimization in (18) will try to reduce BERpage m and make it as close to other page BERs as possible.

(18) is a convex optimization problem since <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M37','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M37">View MathML</a> is a nonnegative weighted sum of convex function Q(·). The convex property of Q(·) was shown in (12). Therefore, the optimal solution can be obtained by several numerical methods.

The Lagrangian G2associated with (18) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M38','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M38">View MathML</a>


where <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M39','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M39">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M40','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M40">View MathML</a>. The optimal solution of (18) has to satisfy the following KKT conditions.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M41','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M41">View MathML</a>


As discussed in criterion 1, all ηks will be zero due to complementary slackness of (21).

Figure 5 shows how criterion 2 works for 2-bit/cell flash memories. In order to make page BERs equal, |μ2μ1| = Δ3 + Δ4 of criterion 2 has to be reduced compared to that of criterion 1. Meanwhile, |μ1μ0| = Δ1 + Δ2 and |μ3μ2| = Δ5 + Δ6 will be larger than those of criterion 1.

thumbnailFigure 5. Example of criterion 2 for 2-bit/cell. This example illustrates the condition which makes page BERs equal and minimizes the overall BER as far as possible.

From (21), we can obtain following conditions for the optimal solution of 2-bit/cell flash memories.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M42','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M42">View MathML</a>


If one of λ s (for m = 0,…,M) is zero, then all λms should be zero since <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M43','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M43">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M44','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M44">View MathML</a> for all k. However, if all λms are zero, the condition of 1−λ1λ2 = 0 in (22) cannot hold. Therefore, we can see that λm ≠ 0, which results in hm ε = 0 by KKT conditions of (21). It means that all page BERs will be equal for the optimal solution of (18) <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M45','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M45">View MathML</a>.

Taking into account the aforementioned discussions, the conditions of (22) can be modified by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M46','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M46">View MathML</a>


which are illustrated in Figure 5.

Figure 6 shows the numerical results of criterion 2 for 2-bit/cell flash memories when variances for all states are equal to σ. All page BERs and the overall BER are made equal by criterion 2. Even if variances for all states are not equal, the optimal solution can be obtained by the same method.

thumbnailFigure 6. BER of 2-bit/cell flash memories using Criterion 2. The constrained voltage window W is assumed to be 5.

It is worth mentioning that the overall BER from criterion 2 is worse than that from criterion 1. The reason is that the overall BER increases when we try to make page BERs equal. Figure 7 shows the degradation of the overall BER from criterion 2 compared to criterion 1 for 2-bit/cell flash memories. In order to measure this degradation, we will define the degradation ratio γ given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M47','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M47">View MathML</a>


thumbnailFigure 7. Comparison between the overall BER from the two criteria. The constrained voltage window W is assumed to be 5.

Figure 8 shows the degradation ratio γ for 2-bit/cell, 3-bit/cell and 4-bit/cell flash memories where we assume that variances for all states are same. For 2-bit/cell, γ is about 1.05, which means that the degradation of the overall BER is 5 %. Meanwhile, the degradation of 3-bit/cell is about 14 % (γ ≈ 1.14) and the degradation of 4-bit/cell is about 25 % (γ ≈ 1.25). These results reveal that equalizing page BERs causes an increase of the overall BER.

thumbnailFigure 8. Degradation ratio γ for 2∼4-bit/cell flash memories. The constrained voltage window W is assumed to be 5.

Verify level control criteria and charge leakage

After programming data into flash memories, the cell threshold voltage distribution can change because of charge leakage. The cell threshold voltage distribution change due to charge leakage can be modeled as a change in the mean and the variance of the distributions, i.e., [6]

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M48','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M48">View MathML</a>


where μpre and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M49','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M49">View MathML</a> are the mean and the variance before charge leakage. μpost and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M50','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M50">View MathML</a> are the mean and the variance after charge leakage. μshift and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M51','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M51">View MathML</a> are the mean and the variance of threshold voltage shift by charge leakage. μshift and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M52','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M52">View MathML</a> depend on the program and erase (P/E) cycle count, retention time and temperature [6].

The proposed verify level control criteria should be applied based on μpost and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M53','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M53">View MathML</a> because μpost and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M54','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M54">View MathML</a> will determine the BER of flash memories. Therefore, we have to control μpre and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M55','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M55">View MathML</a> considering the amount of μshift and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M56','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M56">View MathML</a>. Basically, μpre and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M57','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M57">View MathML</a> can be controlled by verify levels and the incremental step size ΔVpp of ISPP though physical mechanisms such as cell-to-cell interference, program disturbance, and background pattern dependency also affect μpre and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M58','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M58">View MathML</a>[5,7,8].

Via chip testing, we can measure the amount of μshift and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M59','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M59">View MathML</a> as a function of P/E cycle count and retention time [6]. However, the allowable maximum values of μshift and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M60','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M60">View MathML</a> are generally used because ECC has to be designed to guarantee the reliability even in the worst case, which is also called end-of-life (EOL). EOL assumes the allowable maximum P/E cycle count and the allowable maximum retention time. Therefore, it is a practical method to apply the proposed verify level control criteria based on μpost and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M61','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M61">View MathML</a> of EOL. In this case, μpost and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M62','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M62">View MathML</a> should be used to formulate the convex optimization problems shown in (11) and (18). Other than this minor modification, no additional change is required for our proposed mathematical formulations.

Verify level control criteria and other statistical distributions

We will extend these proposed verify level control criteria for other distributions. Suppose that the threshold voltage distribution of each state Si can be approximated as an arbitrary distribution ϕi(x) which has a maximum value at x = νi(i.e., νi is the mode of ϕi(x)). Instead of (2), the constrained voltage window W will be defined by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M63','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M63">View MathML</a>


The distance between Si and Si + 1 will be defined as νi + 1νi instead of μi + 1μi and it is assumed that νi + 1 > νi for all i. In the case of Gaussian distributions, μi and νi are same.

Then, the error probability between Si and Si + 1(i.e., Ei,i + 1) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M64','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M64">View MathML</a>


where P(Si) is the probability of Si. In addition, Δi,1 is the distance from νi to Di,i + 1 and Δi + 1,0 is the distance from νi + 1 to Di,i + 1. Di,i + 1 is the decision level between Si and Si + 1.

Since νi and νi + 1 of (27) are also variables which are determined by <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M65','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M65">View MathML</a>, we will modify (27) as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M66','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M66">View MathML</a>


where ϕi,−(t) = ϕi(t + (νiν0)) and ϕi + 1, + (t) = ϕi + 1(t−(ν2M−1νi + 1)). ν0 and ν2M−1 are fixed value by (26).

The overall BER and the page BERs of M-bit/cell MLC flash memories are nonnegative weighted sums of Ei,i + 1 for i = 0,…,2M−2. Therefore, if Ei,i + 1 is a convex function of Δi,1 and Δi + 1,0, the proposed verify level control criteria will be convex optimization problems.

The Hessian matrix of Ei,i + 1 is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M67','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M67">View MathML</a>


If <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M68','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M68">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M69','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M69">View MathML</a> (i.e., ∇2Ei,i + 1 is positive semidefinite), Ei,i + 1 is a convex function. Therefore, the conditions of ϕi(x) for convex optimization problems are given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M70','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M70">View MathML</a>


which mean that ϕi(x) should be a unimodal distribution for convex optimization.

Since the measured threshold voltage distributions of recent flash memory products [2-4] are unimodal, the proposed verify level control criteria can be effectively applied to flash memories. In addition, the proposed verify level control criteria can be applied to other memories such as phase change memory (PCM) because the measured distributions of PCM in literature seem to be unimodal [26-28]. Especially, [26] claims that the distributions of PCM could be approximated by the log-normal distribution in spite of the anomalous tail. Therefore, our proposed verify level control criteria are expected to be useful in PCM.

ECC and flash memories of multipage architecture

When algebraic ECC such as Bose, Chaudhuri, and Hocquenghem (BCH) codes are used in a binary symmetric channel (BSC) with bit error probability p, the word error rate (WER) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M71','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M71">View MathML</a>


where n is the codeword length and t is the error correcting capability. The bound becomes an equality when the decoder corrects all combinations of errors up to and including t errors, but no combinations of errors greater than t (i.e., bounded distance decoder) [29,30]. In this article, the bounded distance decoder will be considered. Once ECC parameters such as n and t are selected, the WER is a function of only p.

Though errors in flash memories are generally not symmetric, the asymmetric component of errors could be minimized if the decision level are selected appropriately [22-24]. For example, for 2-bit/cell flash memories, the errors of page 1 will be symmetric if we select the decision level <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M72','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M72">View MathML</a> between S1 and S2 which makes <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M73','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M73">View MathML</a> in (6). Similarly, the errors of page 2 can be symmetric if we choose the decision levels <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M74','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M74">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M75','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M75">View MathML</a> which make <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M76','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M76">View MathML</a> and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M77','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M77">View MathML</a> in (6).

In the case of σi = σi + 1, the decision level <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M78','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M78">View MathML</a> which makes the errors symmetric is equal to the optimal decision level Di,i + 1 as follows.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M79','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M79">View MathML</a>


Although σi σi + 1, if σi is not substantially different from σi + 1, the difference between Di,i + 1 and <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M80','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M80">View MathML</a> is almost negligible [22]. Therefore, the BER based on <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M81','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M81">View MathML</a> is similar to that based on Di,i + 1. Considering these, we will use (31) to calculate the WER of flash memories [31].

In most of flash memories, program and read operations are performed in page units [10]. Therefore, ECC encoding and decoding are also performed in page units [13-15]. It means that the WER of each page depends on each page BER which corresponds to p in (31). Therefore, the overall WER is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M82','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M82">View MathML</a>


where WER(BERpage m) is the WER of page m.

Theorem 1

If <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M83','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M83">View MathML</a>, then WER(p) of (31) is a convex function of p.


WER(p) of (31) can be computed from the incomplete beta function Ix(ab) [32].

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M84','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M84">View MathML</a>

The second derivative of WER(p) is given by

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M85','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M85">View MathML</a>

Therefore, <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M86','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M86">View MathML</a> when <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M87','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M87">View MathML</a>. □

Generally, the operation range of ECC satisfies the condition of <a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M88','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M88">View MathML</a>. By the convex property of WER(p) and (33), the following equation holds.

<a onClick="popup('http://asp.eurasipjournals.com/content/2012/1/196/mathml/M89','MathML',630,470);return false;" target="_blank" href="http://asp.eurasipjournals.com/content/2012/1/196/mathml/M89">View MathML</a>


(34) reveals that the overall WER would be improved by interleaving. If the interleaver is applied for the whole data from page 1 to page M, all page BERs will be averaged into the overall BER of (8) and the overall WER would be improved according to (34). In other words, minimizing the overall BER (i.e., criterion 1) is preferred over achieving identical page BERs (i.e., criterion 2), if interleaving is applied.

Actually, the application of interleaving and similar ideas have been proposed in order to resolve the uneven page BER problem and improve the reliability [11,12]. However, the adoption of interleaving will slow down the program and read speed performance because the interleaver should wait to collect at least M pages data before program and read operation in the multipage architecture. Especially, random speed performance would be more degraded than sequential speed performance when employing an interleaver (see Section “Hybrid SSD and strategy for verify level control”).

Therefore, criterion 2 could be a practical alternative for flash memories because it does not degrade the speed performance and exhibits only slight degradation of the overall BER as shown in Figure 8. In addition, criterion 2 does not require large memory buffer for interleaving. Figure 9 shows that the overall WER from criterion 2 is much better than that of criterion 1 without interleaving and only slightly worse than that of criterion 1 with interleaving for 2-bit/cell flash memories.

thumbnailFigure 9. Comparison between the overall WER from criterion1 and from criterion 2 for 2-bit/cell. The BCH code (n = 8752, k = 8192, t = 40) is applied. The constrained voltage window W is assumed to be 5.

However, the WER degradation of criterion 2 will increase as M increases as shown in Figure 10. The reason is that the overall BER from criterion 2 will be much worse than that from criterion 1 for large M as shown in Figure 8. Therefore, criterion 2 would not be appropriate for large M in terms of the reliability.

thumbnailFigure 10. Comparison between the overall WER from criterion1 and from criterion 2 for 2-bit/cell, 3-bit/cell and 4-bit/cell. The BCH code (n = 8752, k = 8192, t = 40) is applied. The constrained voltage window W is assumed to be 5.

Hybrid SSD and strategy for verify level control

In order to reduce the cost of SSD and maintain the speed performance and the durability, the hybrid SSD has been proposed [16,17]. The basic idea is to use both SLC flash memories and MLC (usually 2-bit/cell) flash memories. The SLC flash memory has an edge over the MLC flash memory in terms of the speed performance and the durability. However, the MLC flash memory is cheaper than the SLC flash memory. Therefore, combining them can allow both types of flash memories to complement each other [16-19].

Recently, many flash translation layer (FTL) mapping schemes classify incoming data into hot and cold based on the access frequency and size. If a data is updated frequently, it is referred to as hot, and otherwise cold. Generally, small data are accessed more often, and they are classified as hot data. Meanwhile, cold data correspond to bulk writes at low frequencies [16,18]. The speed performance of SSD is classified into random speed performance and sequential speed performance. The random speed performance is measured in input/output operations per second (IOPS) and the sequential speed performance is measured by transfer rate or throughput such as MB/sec [33]. Considering the characteristics of hot and cold data, we see that the random speed performance is a pivotal factor for hot data and the sequential speed performance is important for cold data.

Figure 11 illustrates the architecture of the hybrid SSD. In this architecture, the hot and cold detection module separates hot data from cold ones dynamically and directs them either to SLC or MLC based on the decision. Before SLC flash memories run out of free blocks, the hybrid SSD performs garbage collection to merge valid cold data of SLC and move them into MLC [18].

thumbnailFigure 11. The architecture of the hybrid SSD [18]. The hot and cold detection module separates hot data from cold ones dynamically.

Based on this architecture of the hybrid SSD, we propose that criterion 1 with interleaving is suitable for storing cold data in MLC because the interleaving would have only a small impact on the sequential speed performance for the cold data access and the garbage collection. Of course, we do not need to consider the verify level control criterion for SLC.

In addition, we can anticipate a lower cost and high density hybrid SSD which combines two types of MLC flash memories. For example, 2-bit/cell may replace SLC and 4-bit/cell may be used in place of 2-bit/cell. Unlike the conventional hybrid SSD which combines SLC and MLC of 2-bit/cell, we have to consider the verify level control criterion for both hot and cold data. We propose that criterion 2 will be appropriate for 2-bit/cell flash memories which mainly deal with hot data. For 4-bit/cell which usually stores cold data, criterion 1 with interleaving will be suitable considering the sequential speed performance and the reliability.


In this article, we investigated the verify level control criteria of ISPP for MLC flash memories. These criteria are formulated and solved by convex optimization. Criterion 1 can minimize the overall BER, however it requires interleaving in multipage architecture which reduces the speed performance. Criterion 2 is suitable for multipage architecture especially for 2-bit/cell flash memories. The problem of criterion 2 is that the error rate degradation will increase for more bits per cell.

Based on these advantages and disadvantages of verify level criteria, we investigated the application of verify level control criteria for the hybrid SSD. By selecting the proper criterion considering the architecture of the hybrid SSD, we can achieve both reliability and speed performance.

The verify level control criteria and the proposed formulation of optimization problems can be extended to other emerging memories such as PCM which are modeled by unimodal distributions.

Competing interests

The authors declare that they have no competing interests.


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